Saw-singulated leadless plastic chip carrier

ABSTRACT

Leadless plastic chip carriers are formed from a matrix of lead frames provided in a section of a metal strip. Each lead frame in the matrix includes a die-attach pad and multiple leads disposed in close proximity to the die-attach pad. After a semiconductor die is attached to each of the die-attach pad and wire-bonded, the leadless plastic chip carriers are formed by providing a plastic encapsulation which exposes the bottom sides of the die-attach pad and the leads. The bottom sides of the leads serve as solder pads to be used for attaching the leadless plastic chip carrier to a printed circuit board.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to integrated circuit packagetechnology. In particular, the present invention relates toresin-encapsulated integrated circuit packages.

[0003] 2. Discussion of the Related Art

[0004] Conventional lead frames are typically formed on a metal stripwhich provides up to ten (10) units. A conventional lead frame includesa “die pad” for accommodating a semiconductor die, and inner leads andouter leads. A lead frame can be incorporated in a variety of integratedcircuit packages, such as a quad flat pack (QFP) package and its manyvariations. In a QFP package, each bond pad provided on thesemiconductor die is wire-bonded to an inner lead which, in turn, iselectrically coupled to an outer lead. The inner leads are typicallyprovided mold-locking features to allow proper positioning of the leadframe during the molding step which provides a plastic or resinencapsulation of the package. After encapsulation, the outer leads aretrimmed and bent using custom trim and form tools to complete theelectrical terminals or “leads” used for mounting the package on to aprinted circuit board. Precise forming of the leads is necessary toensure satisfactory board yield. Malformed leads can result in open orshorted solder joints because of aplanarity or skewed leads. Inaddition, even without such malformed leads, board yield in QFP packagesis also diminished by open solder joints resulting from solder wickingup the leads.

[0005] The size of a prior art QFP package is limited by the dimensionsof the semiconductor die plus about 3 mm on each side. For example, a 7mm×7 mm QFP package can accommodate up to a 4 mm×4 mm semiconductor die.Clearance requirements on a printed circuit board can add another 2 mmon each side to the final foot print. Thus, a 7 mm×7 mm QFP typicallyhas a footprint of 9 mm×9 mm, thereby providing an effective boarddensity of approximately 20%.

[0006] Conventional QFP type packages are encapsulated in resin both atthe top and the bottom of the semiconductor die. Consequently,conventional QFP packages cannot be made thinner than 1.4 mm. Inaddition, external lead “stand-off” requirements add to the height ofthe final printed circuit board assembly.

[0007] One important quality measure for an integrated circuit packageis reliability. In a QFP package, a significant failure mode is thedelamination of the mold compound from the back of a die pad.Delamination introduces moisture into the package and causesmoisture-related failures.

[0008] One performance measure in a conventional QFP or any plasticpackage is thermal performance. Such a package is limited in its thermalperformance because of a lack of a thermally conductive path todissipate heat from the semiconductor die to the exterior. In manyapplications, a heat sink is included in the package. However, includinga heat sink increases the material cost of such a package. Further, evenif a heat sink is included, there are still typically multiple layers ofepoxy through which heat must flow from the semiconductor die to theexterior.

[0009] A conventional QFP package is typically manufactured in anassembly process which requires a custom mold, a custom trim tool and acustom form tool. Thus, the tooling cost for manufacturing a new QFPpackage is high. For a given integrated circuit, rather than providing apackage that is optimized specifically for its size and its number ofinput/output (I/O) terminals, a designer typically selects a package bymatching the size and I/O terminals requirements of his integratedcircuit as closely as possible to one of a few available QFP packagesfor which the tooling investment is already made. Clearly, the resultingQFP package is optimized for neither density nor material cost.

[0010] What is desired is a low cost, high density, high reliabilityintegrated circuit package with flexible configuration.

SUMMARY OF THE INVENTION

[0011] The present invention provides a plastic chip carrier and amethod for making the same. A plastic chip carrier of the presentinvention includes: (a) a semiconductor die with bonding pads formed onits surface; (b) a die-attach pad on which the semiconductor die isattached; (c) leads disposed in close proximity of the die-attach pad;(d) wires bonded to the bonding pads and their corresponding leads toprovide electrical connections; and (e) an encapsulation sealing thesemiconductor die, the die attach-pad, the wires, and the leads from theenvironment in such a manner as to expose only the bottom surfaces ofthe die-attach pad and the leads.

[0012] The plastic chip carrier is formed using a process which includesthe operations: (a) forming a matrix of lead frames out of a metalstrip, with each lead frame having a die-attach pad and leads disposedin close proximity of the die-attach pad; (b) attaching a semiconductordie to each of the die-attach pad of the lead frame; (c) wire-bond thesemiconductor die to the leads, so as to allow the leads to serve aselectrical terminals to the semiconductor die; and (d) encapsulating thedie-attach pad, the semiconductor die, the bond wires and the leads in aresin material to form a package, in such a manner that only the bottomsurface of the die-attach pad and the bottom surfaces of the leads areexposed.

[0013] In one embodiment, the plastic chip carrier has an interlockinglip around the periphery of the die-attach pad, so as to allow theencapsulation material to securely engage the die-attach pad. In anotherembodiment, tie bars are provided attached to the die-attach pad. Eachtie bar extends from the die-attach pad outwards to form a peripheralheat pad at the other end. Heat from the operating semiconductor die isconducted by the tie bar to the heat pad for dissipation out of theencapsulation. One of the heat pads has an appearance distinctive fromthe other heat pads of the chip carrier, thereby providing a convenientmarker on the chip carrier which can be used to identify an orientationof the chip carrier or the location of a specified pin, such as pin 1.

[0014] In one embodiment, the die-attach pad of the plastic chip carrieris pre-plated with palladium to avoid silver migration. In addition, thetop surface of the encapsulation is provided a distinctive pattern,which can be conferred to the encapsulation from the molding cavityduring the molding process. This pattern, which can be a dimple array,for example, can be used to orient the package after singulation.Alternatively, solder balls can be attached to the exposed portions ofthe leads to provide some clearance between the printed circuit board onwhich the package is mounted and the plastic chip carrier. In oneembodiment, a soft solder attaches the semiconductor die to thedie-attach pad to provide improved thermal performance.

[0015] According to another aspect of the present invention, a plasticcarrier includes a double-row lead frame having leads arranged as anannular row of inner leads and an annular row of outer leads. The leadframe includes (a) a die-attach pad; (b) an annular row of inner leads;(c) an annular row of outer leads connected to the annular row of innerleads by a connecting portion. The connecting portion has a thicknesswhich is half the thickness of a lead in the annular rows of inner andouter leads. In one implementation, the leads in the annular row ofinner leads and the annular row of outer leads are arranged in analternating fashion, to allow maximum density for wire bonds from thebonding pads of the semiconductor die at the die-attach pad to the innerand outer leads.

[0016] The double-row frame can be formed in a matrix of substantiallyidentical lead frames. Further, the matrix of lead frames can be formedas one of multiple matrices of lead frames formed in a metal strip.

[0017] The present invention is better understood upon consideration ofdetailed description below and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 shows a strip 100, including six substantially identicalsections 101-1 to 101-6, which can be used to fabricate packages of thepresent invention.

[0019]FIG. 2a shows a 3×3 array of lead frames which can be provided inany of the sections of strip 100.

[0020]FIG. 2b shows lead frame 201 including die-attach pad 202suspended by tie bars 204, which are integrally formed with leads 203.

[0021]FIG. 3 shows FIG. 2a's 3×3 array 200 of lead frames, afterattachment of semiconductor dies to its die attach pads andwire-bonding.

[0022]FIG. 4a shows a molded package 400 in a cross section along onedimension of the die-attach pad.

[0023]FIG. 4b shows a side view of molded package 400.

[0024]FIG. 5a shows a 2×2 array 500 of lead frames, including leadframes 501-1 to 501-4, which can be implemented in a section of strip100, in accordance with another embodiment of the present invention.

[0025]FIG. 5b shows in further detail lead frame 501, which is one oflead frames 501-1 to 501-4 of FIG. 5a.

[0026]FIG. 5c shows a cross section, along line A-A, of die-attach pad502 of FIG. 5b.

[0027]FIG. 5d shows a cross section of a lead in lead frame 501 of FIG.5b.

[0028]FIG. 6a shows a lead frame 600 for a “double-row” SSLPCC, inaccordance with another embodiment of the present invention.

[0029]FIG. 6b shows a cross-section of lead frame 600 of FIG. 6a, alongline A-A of FIG. 6a.

[0030]FIG. 6c shows a cross-section of lead frame 600 of FIG. 6a, alongline B-B of FIG. 6a.

[0031]FIG. 7 shows lines 701, 702 and 703 along which lead frame 600 iscut to sever half-etched portion 606 (thereby severing inner leads 603from outer leads 602) and for severing the leads in inner leads 603 andouter leads 602 from each other.

[0032]FIG. 8a shows a cross-section of a double-row SSLPCC, includinglead frame 600 of FIG. 6a, along line A-A of FIG. 6a.

[0033]FIG. 8b shows a cross-section of a double-row SSLPCC, includinglead frame 600 of FIG. 6a, along line B-B of FIG. 6a

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] The present invention provides a saw-singulated leadless plasticchip carrier (SSLPCC) and a method for assembling such a chip carrier.The SSLPCC of the present invention is a low-cost, high density, highreliability integrated circuit package with superb thermal andelectrical performances. To facilitate cross-reference between figures,in the figures described below, like elements are provided likereference numerals.

[0035]FIG. 1 shows a strip 100 including six substantially identicalsections 101-1 to 101-6, which can be used to fabricate the packages ofthe present invention. Using such a strip allows the assembly process tobe carried out in conventional automated assembly equipment and molds.Within each of sections 101-1 to 101-6 is an area 103 in which leadframes of the present invention can be formed using a conventionalprocess, such as a chemical etching process or a stamping process. A 3×3array of lead frames, labeled 200 in FIG. 2a, can be formed in area 103,as shown in FIG. 2a. On the periphery of area 103 are placed alignmenttargets and tooling through-holes and other conventional features(labeled, collectively, by reference numerals 102 a) used in automatedassembly equipment.

[0036]FIG. 2a shows 3×3 array 200 of lead frames, including lead frames201-1 to 201-9, which can be formed in a section of strip 100. Thus, inthis configuration, 54 lead frames can be formed strip 100. Each leadframe, e.g., lead frame 201-1, includes a die-attach pad (e.g.,die-attach pad 202 a of lead frame 201-1) and a group of leads (e.g.,leads 203 a of lead frame 201-1) provided in close proximity to thedie-attach pad. An exemplary lead frame 201 is shown in further detailin FIG. 2b. As shown in FIG. 2b, lead frame 201 includes die-attach pad202 suspended by tie bars 204, which are integrally formed with leads203. In lead frame 201, tie bars 204 each extend towards the peripheryof lead frame 201 to form a heat pad (e.g., any one of heat pads 208 and209) at one corner of the molded package to be formed. Such a heat padprovides a highly thermally conductive path for transferring heat fromdie-attach pad 202 out of the molded package to be formed. One such heatpad, labeled 208 in FIG. 2b is made slightly different from the otherheat pads (each labeled 209) formed in the other tie bars. In thisembodiment, die-attach pad 202 is 5 mm on a side, and each of leads 203is 0.4 mm wide and 0.13 mm thick. Spacing between adjacent leads is also0.4 mm. Lead frame 201 can be pre-plated with palladium to avoid silvermigration.

[0037] During the assembly process, a singulated semiconductor die isconventionally mounted or attached by epoxy or any suitable adhesive toeach of die-attach pads (e.g., die attach pads 202 a-202 i). Thesemiconductor die can also be attached using a soft solder to providethermal conductivity between the semiconductor die and the die-attachpad, thereby improving the thermal performance of the resulting package.After the adhesive is cured, if required, each semiconductor die iswire-bonded to the leads (e.g., leads 203 a) located at the periphery ofthe die-attach pad, using conventional automated bonding equipment. Goldwires can be used in this wire-bonding operation. FIG. 3 shows 3×3 array200 of FIG. 2b, after die-attachment (note, for example, semiconductordie 206 a) and wire-bonding. Wire-bonds 205 electrically couple eachbonding pad on semiconductor die 206 a to a corresponding one of leads203 a.

[0038] Following wire-bonding, strip 100 is conventionally molded usinga mold in which the bottom plate is a flat plate, so that the moldingcompound exposes the bottom surfaces of the die-attach pads, the heatpads of the tie bars, and the leads. The under side of strip 100 is thendeflashed to remove any molding compound residues from the exposedsurfaces of the lead frames, so as to allow the leads and the die-attachpad to serve as solder pads for attachment to the printed circuit boardat a subsequent time. As mentioned above, one of the heat pads formed onthe tie bars is provided a difference appearance from the other heatpads. This different appearance can serve as a built-in marker toindicate a designated pin (e.g., pin 1) of the package, or to helpidentify an orientation of the package. optionally, strip 100 can thenbe ink-marked and solder-plated to facilitate a subsequent board-attachstep. Solder plating is not necessary if strip 100 was pre-plated withpalladium. Solder balls can also be attached to the exposed portions ofthe leads to provide a clearance when mounted on a printed circuitboard. Such clearance facilitates cleaning (e.g., cleaning of solderflux).

[0039] Finally, strip 100 is mounted to a wafer saw ring by an adhesivetape and saw-singulated using a conventional wafer saw. Singulation canbe guided by a pattern formed on the top side of the package duringmolding. Such a pattern, e.g., a dimple array, which can be easilytransferred from the molding cavity of a mold, is also useful forautomated orienting or positioning of the resulting singulated package.The singulated component is then ready for mounting onto a printedcircuit board. Since no trimming or forming of leads are necessary, inaddition to eliminating the costs associated with such steps, thepackages manufactured under the present method described above do notsuffer yield loss from defective trimming and forming of the externalleads.

[0040]FIG. 4a shows a molded package 400 in a cross section along onedimension of the die-attach pad. As shown in FIG. 4, semiconductor die206 is attached to die-attach pad 202 as described above. Conductivewires 205-1 and 205-2 are bonded to bonding pads on semiconductor die206 and their respective leads 203-1 and 203-2. Molded package 400 isencapsulated in encapsulation material 401. In this embodiment, moldedpackage 400 measures only 1.2 mm thick. A side view of molded package400 is provided in FIG. 4b. FIG. 4b shows heat pads 208 and 209 at thecorners of molded package 400. Since die-attach pad 202, leads 203 andheat pads 208 and 209 are all exposed, the thermal performance of moldedpackage 400 is expected to be much higher than conventional QFPpackages. Since die-attach pad 202 is exposed, the delamination problemof a conventional QFP package is avoided. Further, high reliability canbe further enhanced in molded package 400 if the coefficient ofexpansion of molding material 401 is matched to the coefficient ofexpansion of the printed circuit board to which molded package 400 is tobe mounted.

[0041] Unlike QFP packages of the prior art, because no additionalclearance between packages is needed to accommodate the outer leads, amuch smaller footprint is achievable in molded package 400. For example,in this embodiment, molded package 400 can accommodate up to a 5 mm×5 mmsemiconductor die on a 7 mm×7 mm footprint, thus providing a effectivebond density of 25/49 or almost 50%. Further, since only the top sidesof the die-attach pad and the leads are molded, and since the exposedportions of the leads serve as solder pads, thus obviating the need foradditional lead stand-off, a package of thickness 1.0 mm or less caneasily be achieved. A thin package not only reduces material cost butprovides additional thermal performance also. The relatively short leadsof molded package 400, as compared to the inner leads-outer leadsarrangements of conventional QFP packages, are expected to have lowerparasitics than leads of a conventional QFP package. Thus, a package ofthe present invention provides electrical performance superior to aconventional QFP package. Also, as the manufacturing process describedabove requires little custom tooling, custom packages optimizing todevice size and number of I/O terminals can be accommodated with minimaladditional cost. By avoiding the cost of custom tooling and the cost oftrimming and forming tools, and since molded package 400 requires lessmolding compound and lead frame material, molded package 400 is expectto cost only 10% to 20% of a comparable conventional QFP package.

[0042]FIG. 5a shows a 2×2 array 500 of lead frames, including leadframes 501-1 to 501-4, which can also be implemented in a section ofstrip 100, in accordance with another embodiment of the presentinvention. FIG. 5b shows in further detail lead frame 501, which is oneof lead frames 501-1 to 501-4, showing die-attach pad 502, tie bars 503and leads 504. In this embodiment, an interlocking lip 507 is providedin under side of die-attach pad 502. Interlocking lip 507 is shown inFIG. 5c in the cross section A-A of die-attach pad 502. Interlocking lip507 allows the molding compound to flow underneath a portion of the dieattach pad 502 to securely engage die-attach pad 502 to theencapsulation, thereby preventing moisture introduction into thepackage. FIG. 5d shows a cross section of a lead 504 in lead frame 501of FIG. 5b. As shown in FIG. 5d, an interlocking lip 509, similar tointerlocking lip 507 of die-attach pad 502, is provided in lead 504. Asin interlocking lip 507, interlocking lip 509 allows the moldingcompound to hold lead 504 in place and to prevent introduction ofmoisture into the molded package.

[0043]FIG. 6a shows another embodiment of the present invention in alead frame 600 for a “double row” SSLPCC. As shown in FIG. 6a, leadframe 600 includes a downset die-attach pad 601, which is suspended bytie-bars 607 a-607 d at the four corners of die-attach pad 601. At theother ends of tie bars 607 a-607 d are rectangular pads 604 a-604 c andtriangular pad 605. Rectangular pads 604 a-604 c provide additionalsurfaces for heat dissipation. Triangular pad 605 is designed to be usedfor package orientation, such as indicating the position of pin 1.

[0044] Lead frame 600 includes an annular row of outer leads 602 and anannular row of inner leads 603, initially attached by a half-etchedportion 606—i.e., the inner leads and the outer leads are connected byportion 606 which has a thickness one-half that of the leads.Half-etched portion 606 can be formed by etching the lead frame from thetop using a conventional chemical etching process. In this embodiment,inner leads 603 and outer leads 602 each have a pitch of 0.5 mm, sothat, with each lead being 0.25 mm wide, the spacing between adjacentleads is 0.25 mm. In this embodiment, each lead is 0.618 mm long.Annular inner leads 603 and annular outer leads 603 are positioned in astaggered or alternating manner to allow maximum room for wire-bondingfrom the bonding pads on the surface of a semiconductor die to be placedin die-attach pad 601 to each of the leads. Thus, very high pin densitycan be achieved.

[0045]FIGS. 6b and 6 c shows respectively cross-sections of lead frame600 along lines A-A and B-B. The cross-section shown in FIG. 6b cutsthrough outer leads 602, showing half-etched portion 606, and die-attachpad 601. Similarly, the cross section shown in FIG. 6c cuts throughinner leads 603, showing half-etched portion 606.

[0046] The assembly process for a double-row SSLPCC can follow theassembly process described above. However, in addition to thesingulation step described above, an additional cut to sever half-etchedportion 606 from the lead frame is provided. FIG. 7 shows lines 701, 702and 703 along which lead frame 600 is cut to sever half-etched portion606 (thereby severing inner leads 603 from outer leads 602) and forsevering the leads in inner leads 603 and outer leads 602 from eachother. Line 703 along the outer periphery is the singulation path forsingulating the double-row SSLPCC from the adjacent packages. Line 701and 702 severs half-etched portion 606. Of course, the cuts along lines701 and 702 need only be deep enough to cut through half-etched portion606. Half-etched portion provides clearance to prevent inadvertentdamage to wire bonds between the bonding pads of the semiconductor dieto outer leads 602.

[0047]FIGS. 8a and 8 b show cross sections of a double-row SSPLCCpackage (after singulation) along lines A-A (through outer leads 602)and B-B (through inner leads 603). In this embodiment, the loop heightsof wire bonds 801 and 802 between the semiconductor die 803 to outerleads 602 (FIG. 8b) and to inner leads 603 (FIG. 8a) are 15 mils and 10mils, respectively. (A trapezoidal loop profile can be selected for thewire bonds). For a thickness of 6 mils for each lead in outer leads 602and inner leads 603, a 1 mil die-attach epoxy bondline and a 10 milthick semiconductor die, a 1.2 mm thick package would provide a 15 milclearance between the top of each bond wire loop to the top of thepackage. Half-cut to sever connecting portion 606 can be made to a depthof 5 mils.

[0048] The above detailed description is provided to illustrate thespecific embodiments of the present invention and is not intended to belimiting. Numerous modifications and variations within the scope of thepresent invention are possible. The present invention is particularlypointed out and distinctly claimed in the following claims.

We claim:
 1. A plastic chip carrier, comprising: a semiconductor diehaving bonding pads formed thereon; a die-attach pad having a bottomsurface and a top surface on which said semiconductor die is attached; aplurality of leads, each having a bottom surface and a top surface, saidleads disposed in close proximity to said die-attach pad; a plurality ofwires each bonded to a selected one of said bonding pads and acorresponding one of said leads; and an encapsulation encapsulating saidsemiconductor die, said top surface of said die attach-pad, said wires,and said top surfaces of said leads, and exposing said bottom surface ofsaid die-attach pad and said bottom surfaces of said leads.
 2. A plasticchip carrier as in claim 1 , wherein said die-attach pad is provided aninterlocking lip at a portion of said die-attach pad, said interlockinglip engaging said die-attach pad to said encapsulation.
 3. A plasticchip carrier as in claim 1 , further comprising a plurality of tie bars,each tie bar being attached to said die-attach pad and extending fromsaid die-attach pad to form a peripheral heat pad for dissipating heatto the outside of said encapsulation.
 4. A plastic chip carrier as inclaim 3 , wherein one of said heat pads has an appearance distinctivefrom other heat pads of said chip carrier.
 5. A plastic carrier as inclaim 1 , wherein said die-attach pad and said leads are formed out ofan array of lead frames integrally formed on a portion of a metal strip.6. A plastic carrier as in claim 1 , wherein said die-attach pad isplated with palladium.
 7. A plastic carrier as in claim 1 , wherein adistinctive pattern is formed on said encapsulation.
 8. A plasticcarrier as in claim 1 , further comprising solder balls each attached toa bottom side of a corresponding one of said leads.
 9. A plastic carrieras in claim 1 , wherein a soft solder attaches said semiconductor die tosaid die-attach pad.
 10. A plastic carrier as in claim 1 , wherein saidplurality of leads are arranged as an annular row of inner leads and anannular row of outer leads.
 11. A process for forming a plastic carrier,comprising: forming a matrix of lead frames out of a metal strip, eachlead frame including a die-attach pad and a plurality of leads disposedin close proximity to said die-attach pad, said die-attach pad and saidleads each having a bottom surface and a top surface; attaching to thetop surface of each die-attach pad a semiconductor die, saidsemiconductor die having a plurality of bonding pads formed thereon;providing bond wires to electrically connect each of said bonding padsto the top surface of a corresponding lead; and encapsulating saiddie-attach pad, said semiconductor die, said bond wires and said leadsin a resin material such that said bottom surface of said die-attach padand said bottom surfaces of said leads are exposed.
 12. A process as inclaim 11 , wherein said die-attach pad is provided an interlocking lipat the periphery such that said resin material engages interlocking lipof said die-attach pad.
 13. A process as in claim 11 , wherein each ofsaid lead frames includes tie bars, said matrix of lead frames beingformed with each tie bar being attached to said die-attach pad andextending from said die-attach pad to form a peripheral heat pad fordissipating heat.
 14. A process as in claim 13 , wherein one of saidheat pads has an appearance distinctive from other heat pads in saidlead frame.
 15. A process as in claim 11 , further comprising theoperation of plating said die-attach pad with palladium.
 16. A processas in claim 11 , wherein a distinctive pattern is formed on said resinmaterial by said encapsulating step.
 17. A process as in claim 11 ,further comprising the operation of attaching solder balls to the bottomsides of corresponding leads.
 18. A process as in claim 11 , whereinsaid attaching step provides a soft solder to attach said semiconductordie to said die-attach pad.
 19. A lead frame, comprising: a die-attachpad; an annular row of inner leads; an annular row of outer leadsconnected to said annular row of inner leads by a connecting portion,wherein said die-attach pad is connected to said annular row of innerleads and said annular row of outer leads by a plurality of tie bars.20. A lead frame as in claim 19 , wherein said connecting portion has athickness which is half the thickness of a lead in said annular row ofinner leads.
 21. A lead frame as in claim 19 , wherein leads in saidannular row of inner leads and said annular row of outer leads arearranged in an alternating fashion.
 22. A lead frame as in claim 19 ,wherein said lead frame is a lead frame within a matrix of substantiallyidentical lead frames, and said matrix being one of multiple matrices oflead frames formed in a metal strip.